If you want definitive information on how Cortex-M cores work then you will have to refer to the hardware manuals provided by ARM.
As for the paragraph you highlight, I’m struggling to see an inconsistency, so don’t fully understand the point you are making.
BASEPRI is a bit mask. Setting BASEPRI to a value masks all interrupts
that have a priority at and (logically) below that value.
So, ignoring the confusing bit shifts for a moment and just dealing with logical priorities, if the lowest possible priority is 15 and you set BASEPRI to 10, then “at or logically below” would mean priorities 10, 11, 12, 13, 14 and 15 would be masked. Priority 0, being the highest priority would not be masked.
It is therefore not possible to use BASEPRI to mask interrupts that
have a priority of 0
You can write bits into BASEPRI to mask interrupt priorities. As priority 0 does not have any bits set, you cannot write bits into BASEPRI to mask it.