I’m new to FreeRTOS, I’m working on a project that was developed using XiLinx. There are two parts to this project, an FPGA and an Application. The FPGA and Application use share memory to communicate. I have the original source code but its very unclear how this works and why it works at all. The application declares a pointer to an address that as far as I can see is not allocated or protected in any way, this pointer is at 0x43c00000. In the application this address is use as follows:

    volatile AxiAddressMapping* currentAxiMapping = (AxiAddressMapping*)AXI_ADDRESS_MAPPING;

The application then reads and writes to this structure. There isn’t any protection or API calls I can see in place to determine how this memory is accessed or protects either side. When this memory is access the application crashes. Is there an example on the correct way to do this?

I believe I was very wrong in what I posted I can see now that the FPGA and the Application communicate via a Queue which is protected by semaphore. The memory location in my original post sill causes a crash and I can see no evidence of how this could have worked. I’m looking at the datasheets for the orignal board: Zynq – 7000 Development Board And the new board: Zynq – 7010 Development Board.

I believe I was very wrong in what I posted I can see now that the FPGA and the Application communicate via a Queue which is protected by semaphore. The memory location in my original post sill causes a crash and I can see no evidence of how this could have worked. I’m looking at the datasheets for the orignal board: Zynq – 7000 Development Board And the new board: Zynq – 7010 Development Board.

In fact the FPGA design contains an AXI lite port mapped to a physical address range starting at this fixed address. The FPGA code in turn handles read/write accesses to this address range by the CPU. That’s low level and is completely up to your application code. I’m not familiar with the FreeRTOS Zynq port, but there should be some PS (processing system) init code called early setting up the PS including memory/address regions etc. generated by the Xilinx FPGA toolchain (ps7init.c ?). I assume the FPGA is already loaded when running your application. Otherwise the AXI bus access will fail probably causing a HW exception.

And someone also ported the FPGA design to the new board 😉 Perhaps there are some debug LEDs showing that the FPGA was successfully initialized…

That address is in the address space of the I/O bus of the FPGA. When you code accesses that, it will do an AXI access to talk to the FPGA. If the FPGA isn’t initialized, still in reset, or isn’t getting a clock, you will get a bus error. On the Zynq, as I remember the processor comes up first and is responsible for configuring the FPGA, and if it tries to access the FPGA before it has finished initializing you will get this sort of error. If you altered the FPGA design, it is also possible that your port changed to a different address, as the address is based on bus position, and if you change that the address will be different.

It gets stranger, the original post was partly correct in that the FPGA and Application use it for communication and general communication between the two apps is via the queues. The odd thing is that Xilinx 2019.1 when used results in a crash as soon as this memory location is accessed. Xilinx 2016.2 works fine, its exactly the same source just compiled using different versions of Xilinx.

Welcome in the world of the Xilinx toolchains 😉