I am using SafeRTOS on the Stellaris LM3S9B96.   I know there is a forum for SafeRTOS and LM3S9B96, but I thought the FreeRTOS community would have some insight into my questions. The macros (portSET_INTERRUPT_MASK(), portCLEAR_INTERRUPT_MASK()) to disable and enable interrupts in portmacro.h “clobbers r0”, as the comments in the code indicate.  I have noticed that recent versions of FreeRTOS push r0 on to the stack and pop it off afterwards, hence, r0 is not “clobbered”.  Did older versions of FreeRTOS for Cortex-M3 “clobber” r0?  Since the macro is a C macro with inline assembler, will “clobbering” r0 interfere with the compiler’s generation of code (I know that the question is slightly dependant on the compiler). Basically, I am wondering if anyone has some insight to this and whether “clobbering” r0 is known to be an issue.  Though I could rewrite the macro in portmacro.h to not “clobber” r0, I am sure the SafeRTOS version burned into ROM must be using the same code and hence “clobbering” r0 already.

I have just had a quick glance at the code, and think the SafeRTOS version is doing exactly the right thing with regards to containing r0 in the clobber list.  If it were a function it would not be necessary, but because it is a macro, it is. Now having just looked at the FreeRTOS version of the same macro, it looks to me to be identical to the SafeRTOS version with its use of the clobber list (in the inline asm).  Maybe you are looking at a different version of FreeRTOS? In any case, whether you add it to a clobber list and let the compiler sort it out, or whether you push and pop r0 manually, should not make any difference to the correctness of the code.  Letting the compiler do it (using the clobber list) would be the better way though as it allows the compiler to perform better optimisation (by, for example, not using r0 for anything else around the call to the macro). Regards.

I believe I am looking at the source code for the CCS4 port – which I realize is contributed and hence not officially supported.  The port chooses to use the following in portasm.asm: ;————————————– vPortSetInterruptMask: push { r0 }
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY                    
msr basepri, r0    
pop { r0 }
bx r14 ;————————————– vPortClearInterruptMask: push { r0 }
mov r0, #0
msr basepri, r0
pop { r0 }
bx r14 Based on what you are saying, it sounds like the compiler should handle it – but perhaps someone knows for sure whether the TI Compiler has any issues, hence the push and pop on the CCS port?

The compiler will only handle it if you tell it it needs to handle it.  i.e. you add the clobbered register to the clobber list. Clobber lists in that sense are a very sophisticated feature of the GCC inline assembler, and I doubt the code composer compiler has an equivalent.  In which case, the push and pop will be necessary. Regards.